33874 Datasheet, PDF (18/37 Pages) Freescale Semiconductor, Inc – Quad High-Side Switch (Quad 35 mΩ)

FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSTIC FEATURES
resistance limiting the internal clamp current according to the
specification.
The Watchdog timeout is a multiple of an internal oscillator
and is specified in the Table 15, page 23. As long as the WD
bit (D15) of an incoming SPI message is toggled within the
minimum watchdog timeout period (WDTO), based on the
programmed value of the WDR, the device will operate
normally. If an internal watchdog timeout occurs before the
WD bit, the device will revert to a Fail-Safe mode until the
device is reinitialized.
During the Fail-Safe mode, the outputs will be ON or OFF
depending upon the resistor RFS connected to the FSI pin,
regardless of the state of the various direct inputs and modes
(Table 6).
Table 6. Output State During Fail-Safe Mode
RFS (kΩ)
High-Side State
0 (shorted to ground)
6.0
15
30 (open)
Fail-Safe Mode Disabled
All HS OFF
HS0 ON
HS1 : HS3 OFF
HS0 and HS2 ON
HS1 and HS3 OFF
In the Fail-Safe mode, the SPI register content is retained
except for overcurrent high and low detection levels, timing
and latched overtemperature which are reset to their default
value (SOCL, SOCH, and OCTL and OT_latch_[0:3] bits). Then
the watchdog, overvoltage, overtemperature, and
overcurrent circuitry (with default value) are fully operational.
The Fail-Safe mode can be detected by monitoring the
WDTO bit D2 of the WD register. This bit is logic [1] when the
device is in Fail-Safe mode. The device can be brought out of
the Fail-Safe mode by transitioning the WAKE and RST pins
from logic [1] to logic [0] or forcing the FSI pin to logic [0].
Table 5 summarizes the various methods for resetting the
device from the latched Fail-Safe mode.
If the FSI pin is tied to GND, the Watchdog fail-safe
operation is disabled.
LOSS OF V_DD
If the external 5.0 V supply is not within specification, or
even disconnected, all register content is reset. The outputs
can still be driven by the direct inputs IN0 : IN3. The 33874
uses the battery input to power the output MOSFET-related
current sense circuitry and any other internal logic providing
fail-safe device operation with no V_DD supplied. In this state,
the watchdog, undervoltage, overvoltage, overtemperature
(latched) and overcurrent circuitry are fully operational with
default values.
FAULT MODE
This 33874 indicates the faults below as they occur by
driving the FS pin to logic [0]:
• Overtemperature fault
• Overvoltage and undervoltage fault
• Open load fault
• Overcurrent fault (high and low)
The FS pin will automatically return to logic [1] when the
fault condition is removed, except for overcurrent,
overtemperature (in case of latching configuration) and in
some cases of undervoltage.
The FS pin reports all faults. For latched faults, this pin is
reset by a new Switch ON command (via SPI or direct input
IN).
Fault information is retained in the fault register and is
available (and reset) via the SO pin during the first valid SPI
communication (refer to Table 17, page 25).
PROTECTION AND DIAGNOSTIC FEATURES
OVERTEMPERATURE FAULT (LATCHING OR
NON-LATCHING)
The 33874 incorporates overtemperature detection and
shutdown circuitry for each output structure.
The overtemperature is latched per default and can be
unlatched through SPI with OT_latch_[0:3] bits.
An overtemperature fault condition results in turning OFF
the corresponding output. To remove the fault and be able to
turn ON again the outputs, the failure must be removed and:
• in Normal Mode: the corresponding output must be
commanded OFF and ON again in case of
overtemperature latched (OT_latch bit = 0).
• in Normal Mode: the corresponding output turns ON
automatically if the temperature is below T_SD-T_SD(HYS) in
case of unlatched overtemperature (OT_latch bit = 1).
• in Fail-Safe Mode: the FSI input must be grounded and
then set to its nominal voltage to switch ON the outputs.
The overtemperature fault (one for each output) is
reported by SPI. If the overtemperature is latched, the SPI
reports OTF_s = [1] and OCLF_s = [1]. In case of non-
latched, OTF_s = [1] only is reported.
The fault bits will be cleared in the status register after either
a valid SPI read command or a power on reset of the device.
OVERCURRENT FAULT (LATCHING)
The 33874 has eight programmable overcurrent low
detection levels (I_OCL) and two programmable overcurrent
high detection levels (I_OCH) for maximum device protection.
The two selectable, simultaneously active overcurrent
33874
18
Analog Integrated Circuit Device Data
Freescale Semiconductor