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MC9S12H256VFVE Datasheet, PDF (88/130 Pages) Freescale Semiconductor, Inc – Original Release Date: 29 SEP 2000 Revised: 28 JUL 2008 | |||
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MC9S12H256 Device User Guide â V01.20
Table 21-1 Recommended Components
Component
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
R1
Q1
Purpose
VDD1 ï¬lter cap
VDDA ï¬lter cap
VDDX2 ï¬lter cap
VDDR ï¬lter cap
VDDM3 ï¬lter cap
VDDM2 ï¬lter cap
VDDM1 ï¬lter cap
VDDX1 ï¬lter cap
VDDPLL ï¬lter cap
OSC load cap
OSC load cap
PLL loop ï¬lter cap
PLL loop ï¬lter cap
DC cutoff cap
PLL loop ï¬lter res
Quartz/Resonator
Type
ceramic X7R
X7R/tantalum
X7R/tantalum
X7R/tantalum
X7R/tantalum
X7R/tantalum
X7R/tantalum
X7R/tantalum
ceramic X7R
Value
100 .. 220nF
>=100nF
>=100nF
>=100nF
>=100nF
>=100nF
>=100nF
>=100nF
100nF .. 220nF
See CRG Block User Guide
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
⢠Every supply pair must be decoupled by a ceramic/tantalum capacitor connected as near as possible
to the corresponding pins(C1 â C9).
⢠Central point of the ground star should be the VSS1 pin.
⢠Use low ohmic low inductance connections between VSS1, VSS2, VSSA, VSSX1,2 and
VSSM1,2,3.
⢠VSSPLL must be directly connected to VSS1.
⢠Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C10,
C11, C14 and Q1 as small as possible.
⢠Do not place other signals or supplies underneath area occupied by C10, C11, C14 and Q1 and the
connection area to the MCU.
⢠Central power input should be fed in at the VDDA/VSSA pins.
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