MC9S12H256VFVE Datasheet, PDF (2/130 Pages) Freescale Semiconductor, Inc – Original Release Date: 29 SEP 2000 Revised: 28 JUL 2008

Revision History
DOCUMENT NUMBER
9S12H256BDGV1/D
Version Revision Effective
Number Date
Date
V01.00
07 MAR 03 APR
2001
2001
V01.01
10 MAI
2001
10 MAY
2001
V01.02
V01.03
V01.04
V01.05
14 MAY
2001
30 MAY
2001
11 JUN
2001
18 JUN
2001
14 MAY
2001
30 MAY
2001
11 JUN
2001
18 JUN
2001
V01.06
28 JUN
2001
28 JUN
2001
V01.07
12 JUL
2001
12 JUL
2001
V01.08
V01.09
V01.10
16 JUL
2001
03 AUG
2001
29 AUG
2001
16 JUL
2001
03 AUG
2001
29 AUG
2001
Author
Description of Changes
Initial version.
- Minor formal corrections
- Changed ATD coupling ratio to10^-2
- Changed V_DD5 to 4.5V
- Removed 112-pin package references
- Changed ATD Electrical Characteristics separate coupling ratio for
positive and negative bulk current injection
- Reinserted 112-pin package information.
- Removed SRSv2 comment from preface
- Corrected RESET pin to active low in table 2-1
- Adapted style and wording to 9DP256 device user guide
- Minor format and wording improvements
- Added SRAM data retention disclaimer
- Changed Oscillator Characteristics t_CQOUT max 2.5s and replaced
Clock Monitor Time-out by Clock Monitor Failure Assert Frequency
- Changed Self Clock Mode Frequency min 1MHz and max 5.5MHz
- Changed I_DDPS (RTI and COP disabled) to 400µA
- Corrected typo in Figure 2-1 pin 76: PK3 -> PK2
- Added t_EXTR and t_EXTF to Oscillator Characteristics
- Added typ value for t_UPOSC
- Corrected t_EXTL and t_EXTH values
- Updated thermal resistances as per Thermal Simulation Report,
July 10, 2001
- updated EEPROM size
- added DC cutoff capacitor into layout proposals
- minor updates
- updated electrical spec
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