MC9S12H256VFVE Datasheet, PDF (79/130 Pages) Freescale Semiconductor, Inc – Original Release Date: 29 SEP 2000 Revised: 28 JUL 2008

Section 5 Resets and Interrupts
MC9S12H256 Device User Guide — V01.20
5.1 Overview
Consult the Exception Processing section of the HCS12 Core User Guide for information on resets and
interrupts.
5.2 Vectors
5.2.1 Vector Table
Table 5-1 lists interrupt sources and vectors in default order of priority.
Table 5-1 Reset and Interrupt Vector Table
Vector Address
Interrupt Source
CCR
Mask
Local Enable
$FFFE, $FFFF
External or Power On Reset None
None
$FFFC, $FFFD
Clock Monitor fail reset
None COPCTL (CME, FCME)
$FFFA, $FFFB
COP failure reset
None
COP rate select
$FFF8, $FFF9 Unimplemented instruction trap None
None
$FFF6, $FFF7
SWI
None
None
$FFF4, $FFF5
XIRQ
X-Bit
None
$FFF2, $FFF3
IRQ
I-Bit
INTCR (IRQEN)
$FFF0, $FFF1
Real Time Interrupt
I-Bit
RTICTL (RTIE)
$FFEE, $FFEF
Timer channel 0
I-Bit
TIE (C0I)
$FFEC, $FFED
Timer channel 1
I-Bit
TIE (C1I)
$FFEA, $FFEB
Timer channel 2
I-Bit
TIE (C2I)
$FFE8, $FFE9
Timer channel 3
I-Bit
TIE (C3I)
$FFE6, $FFE7
Timer channel 4
I-Bit
TIE (C4I)
$FFE4, $FFE5
Timer channel 5
I-Bit
TIE (C5I)
$FFE2, $FFE3
Timer channel 6
I-Bit
TIE (C6I)
$FFE0, $FFE1
Timer channel 7
I-Bit
TIE (C7I)
$FFDE, $FFDF
Timer overflow
I-Bit
TSCR2 (TOI)
$FFDC, $FFDD Pulse accumulator A overflow I-Bit
PACTL (PAOVI)
$FFDA, $FFDB Pulse accumulator input edge I-Bit
PACTL (PAI)
$FFD8, $FFD9
SPI
I-Bit
SPICR1 (SPIE)
$FFD6, $FFD7
SCI0
I-Bit
SC0CR2
(TIE, TCIE, RIE, ILIE)
$FFD4, $FFD5
SCI1
I-Bit
SC1CR2
(TIE, TCIE, RIE, ILIE)
$FFD2, $FFD3
ATD
I-Bit
ATDCTL2 (ASCIE)
$FFD0, $FFD1
Reserved
$FFCE, $FFCF
Port J
I-Bit
PTJIF (PTJIE)
$FFCC, $FFCD
Port H
I-Bit
PTHIF (PTHIE)
$FFCA, $FFCB
Reserved
HPRIO Value
to Elevate
-
-
-
-
-
-
$F2
$F0
$EE
$EC
$EA
$E8
$E6
$E4
$E2
$E0
$DE
$DC
$DA
$D8
$D6
$D4
$D2
$CE
$CC
79