MC9S08DN60 Datasheet, PDF (86/354 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 6 Parallel Input/Output Control
6.5.1.7 Port A Interrupt Pin Select Register (PTAPS)
R
W
Reset:
7
PTAPS7
0
6
PTAPS6
5
PTAPS5
4
PTAPS4
3
PTAPS3
2
PTAPS2
1
PTAPS1
0
0
0
0
0
0
Figure 6-9. Port A Interrupt Pin Select Register (PTAPS)
Table 6-7. PTAPS Register Field Descriptions
0
PTAPS0
0
Field
Description
7:0
Port A Interrupt Pin Selects — Each of the PTAPSn bits enable the corresponding port A interrupt pin.
PTAPS[7:0] 0 Pin not enabled as interrupt.
1 Pin enabled as interrupt.
6.5.1.8 Port A Interrupt Edge Select Register (PTAES)
R
W
Reset:
7
PTAES7
0
6
PTAES6
5
PTAES5
4
PTAES4
3
PTAES3
2
PTAES2
0
0
0
0
0
Figure 6-10. Port A Edge Select Register (PTAES)
Table 6-8. PTAES Register Field Descriptions
1
PTAES1
0
0
PTAES0
0
Field
Description
7:0
PTAES[7:0]
Port A Edge Selects — Each of the PTAESn bits serves a dual purpose by selecting the polarity of the active
interrupt edge as well as selecting a pull-up or pull-down device if enabled.
0 A pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation.
1 A pull-down device is connected to the associated pin and detects rising edge/high level for interrupt
generation.
MC9S08DN60 Series Data Sheet, Rev 2
86
Freescale Semiconductor