MC9S08DN60 Datasheet, PDF (324/354 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
A.12.3 SPI
Table A-15 and Figure A-7 through Figure A-10 describe the timing requirements for the SPI system.
Table A-15. SPI Electrical Characteristic
Num¹ C
Rating²
Symbol
Min
Max
Unit
Cycle time
1
D
Master t_SCK
2
Slave _tSCK
4
2048
t_cyc
—
t_cyc
Enable lead time
2
D
Master _tLead
—
Slave _tLead
1/2
1/2
t_SCK
—
t_SCK
Enable lag time
3
D
Master _tLag
—
Slave _tLag
1/2
1/2
t_SCK
—
t_SCK
4
D
Clock (SPSCK) high time
Master and Slave
t_SCKH
(1/2 t_SCK )– 25
—
ns
Clock (SPSCK) low time
5
D
Master and Slave _tSCKL (1/2 t_SCK) – 25
—
ns
Data setup time (inputs)
6
D
Master _tSI(M)
30
Slave _tSI(S)
30
—
ns
—
ns
Data hold time (inputs)
7
D
Master _tHI(M)
30
Slave _tHI(S)
30
8
D Access time, slave³
t_A
0
9
D Disable time, slave⁴
t_dis
—
—
ns
—
ns
40
ns
40
ns
Data setup time (outputs)
10
D
Master _tSO
25
Slave _tSO
25
—
ns
—
ns
Data hold time (outputs)
11
D
Master _tHO
–10
Slave _tHO
–10
—
ns
—
ns
Operating frequency⁵
12
D
Master f_op
Slave _fop
f_Bus/2048
dc
5
f_Bus/4
MHz
1 _{Refer to Figure A-7 through Figure A-10.}
2 _{All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI}
pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output
pins.
3 _{Time to data active from high-impedance state.}
4 _{Hold time to high-impedance state.}
5 _{Maximum baud rate must be limited to 5 MHz due to pad input characteristics.}
MC9S08DN60 Series Data Sheet, Rev 2
324
Freescale Semiconductor