MC9S08DN60 Datasheet, PDF (266/354 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 15 Timer/PWM Module (S08TPMV3)
When a channel is configured for edge-aligned PWM (CPWMS=0, MSnB=1 and ELSnB:ELSnA not =
0:0), the data direction is overridden, the TPMxCHn pin is forced to be an output controlled by the TPM,
and ELSnA controls the polarity of the PWM output signal on the pin. When ELSnB:ELSnA=1:0, the
TPMxCHn pin is forced high at the start of each new period (TPMxCNT=0x0000), and the pin is forced
low when the channel value register matches the timer counter. When ELSnA=1, the TPMxCHn pin is
forced low at the start of each new period (TPMxCNT=0x0000), and the pin is forced high when the
channel value register matches the timer counter.
TPMxMODH:TPMxMODL = 0x0008
TPMxMODH:TPMxMODL = 0x0005
TPMxCNTH:TPMxCNTL ... 0 1 2 3 4 5 6 7 8 0 1 2 ...
TPMxCHn
CHnF BIT
TOF BIT
Figure 15-3. High-True Pulse of an Edge-Aligned PWM
TPMxMODH:TPMxMODL = 0x0008
TPMxMODH:TPMxMODL = 0x0005
TPMxCNTH:TPMxCNTL ...
TPMxCHn
01
2 3 45 6
780
1 2 ...
CHnF BIT
TOF BIT
Figure 15-4. Low-True Pulse of an Edge-Aligned PWM
MC9S08DN60 Series Data Sheet, Rev 2
266
Freescale Semiconductor