MC9S08DN60 Datasheet, PDF (73/354 Pages) Freescale Semiconductor, Inc – Microcontrollers

Field
2
LOC
1
LVD
Chapter 5 Resets, Interrupts, and General System Control
Table 5-3. SRS Register Field Descriptions
Description
Loss of Clock — Reset was caused by a loss of external clock.
0 Reset not caused by loss of external clock
1 Reset caused by loss of external clock
Low-Voltage Detect — If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset will
occur. This bit is also set by POR.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
5.8.3 System Background Debug Force Reset Register (SBDFR)
This high page register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
BDFR¹
Reset:
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
1 _{BDFR is writable only through serial background debug commands, not from user programs.}
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
Table 5-4. SBDFR Register Field Descriptions
Field
0
BDFR
Description
Background Debug Force Reset — A serial background command such as WRITE_BYTE can be used to allow
an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program.
MC9S08DN60 Series Data Sheet, Rev 2
Freescale Semiconductor
73