MC9S08DN60 Datasheet, PDF (320/354 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
Table A-12. MCG Frequency Specifications (Temperature Range = –40 to 125°C Ambient) (continued)
Num C
20 D Lock time - FLL
Rating
21 D Lock time - PLL
Loss of external clock minimum frequency - RANGE =
22 D 0
Symbol
t_{fll_lock}
t_{pll_lock}
f_{loc_low}
Min
—
—
Typical
Max
—
t_{fll_acquire+}
1075(1/^fint_t)
—
t_{pll_acquire+}
1075(1/^fpll_ref)
Unit
s
s
(3/5) x f_int
—
—
kHz
Loss of external clock minimum frequency - RANGE =
23 D 1
f_{loc_high}
(16/5) x f_int
—
—
kHz
1 _{TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).}
2 _{This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing}
from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
3 _{This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE,}
BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already
running.
4 _{Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS.}
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected
into the FLL circuitry via V_DD and V_SS and variation in crystal oscillator frequency increase the C_Jitter percentage for a given
interval.
5 _{Jitter measurements are based upon a 48 MHz MCGOUT clock frequency.}
6 _{625 ns represents 5 time quanta for CAN applications, under worst case conditions of 8 MHz CAN bus clock, 1 Mbps CAN bus}
speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a synchronization edge and the
sample point of a bit using 8 time quanta per bit.
7 _{Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But if the MCG}
is already in lock, then the MCG may stay in lock.
8 _{Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit lock.}
MC9S08DN60 Series Data Sheet, Rev 2
320
Freescale Semiconductor