MC9S08DN60 Datasheet, PDF (136/354 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 8 Multi-Purpose Clock Generator (S08MCGV1)
Table 8-4. MCG Status and Control Register Field Descriptions (continued)
Field
Description
1
OSCINIT
0
FTRIM
OSC Initialization — If the external reference clock is selected by ERCLKEN or by the MCG being in FEE, FBE,
PEE, PBE, or BLPE mode, and if EREFS is set, then this bit is set after the initialization cycles of the external
oscillator clock have completed. This bit is only cleared when either EREFS is cleared or when the MCG is in
either FEI, FBI, or BLPI mode and ERCLKEN is cleared.
MCG Fine Trim — Controls the smallest adjustment of the internal reference clock frequency. Setting FTRIM
will increase the period and clearing FTRIM will decrease the period by the smallest amount possible.
If an FTRIM value stored in nonvolatile memory is to be used, it’s the user’s responsibility to copy that value from
the nonvolatile memory location to this register’s FTRIM bit.
8.3.5 MCG Control Register 3 (MCGC3)
7
6
5
4
3
2
1
0
R
0
LOLIE
PLLS
CME
W
VDIV
Reset:
0
0
0
0
0
0
0
1
Figure 8-7. MCG PLL Register (MCGPLL)
Table 8-5. MCG PLL Register Field Descriptions
Field
7
LOLIE
6
PLLS
Description
Loss of Lock Interrupt Enable — Determines if an interrupt request is made following a loss of lock indication.
The LOLIE bit only has an effect when LOLS is set.
0 No request on loss of lock.
1 Generate an interrupt request on loss of lock.
PLL Select — Controls whether the PLL or FLL is selected. If the PLLS bit is clear, the PLL is disabled in all
modes. If the PLLS is set, the FLL is disabled in all modes.
1 PLL is selected
0 FLL is selected
MC9S08DN60 Series Data Sheet, Rev 2
136
Freescale Semiconductor