MC9S08DN60 Datasheet, PDF (175/354 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Analog-to-Digital Converter (S08ADC12V1)
R
W
Reset:
7
ADR7
0
6
ADR6
5
ADR5
4
ADR4
3
ADR3
2
ADR2
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-7. Data Result Low Register (ADCRL)
1
ADR1
0
0
ADR0
0
10.3.5 Compare Value High Register (ADCCVH)
In 12-bit mode, the ADCCVH register holds the upper four bits of the 12-bit compare value. These bits are
compared to the upper four bits of the result following a conversion in 12-bit mode when the compare
function is enabled.
7
6
5
4
R
0
0
0
0
W
Reset:
0
0
0
0
= Unimplemented or Reserved
3
ADCV11
2
1
ADCV10 ADCV9
0
ADCV8
0
0
0
0
Figure 10-8. Compare Value High Register (ADCCVH)
In 10-bit mode, the ADCCVH register holds the upper two bits of the 10-bit compare value (ADCV9 –
ADCV8). These bits are compared to the upper two bits of the result following a conversion in 10-bit mode
when the compare function is enabled.
In 8-bit mode, ADCCVH is not used during compare.
10.3.6 Compare Value Low Register (ADCCVL)
This register holds the lower 8 bits of the 12-bit or 10-bit compare value, or all 8 bits of the 8-bit compare
value. Bits ADCV7:ADCV0 are compared to the lower 8 bits of the result following a conversion in 12-bit,
10-bit or 8-bit mode.
7
R
ADCV7
W
Reset:
0
6
ADCV6
5
ADCV5
4
ADCV4
3
ADCV3
2
ADCV2
1
ADCV1
0
0
0
0
0
0
Figure 10-9. Compare Value Low Register(ADCCVL)
0
ADCV0
0
10.3.7 Configuration Register (ADCCFG)
ADCCFG is used to select the mode of operation, clock source, clock divide, and configure for low power
or long sample time.
MC9S08DN60 Series Data Sheet, Rev 2
Freescale Semiconductor
175