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MC68181 Datasheet, PDF (78/119 Pages) Freescale Semiconductor, Inc – Advance Information ROAMING FLEX chip SIGNAL PROCESSOR
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MC68181
Freescale Semiconductor, Inc.
Host-to-Decoder Packet Descriptions
Timing Control Packet
The timing control packet gives the host control of the timing used when FLEX chip is
in asynchronous mode. The packet ID for the timing control packet is 6.
Table 2-12 Timing Control Packet Bit Assignments
Byte
3
2
1
0
Bit 7
0
0
AST7
ABT7
Bit 6
0
0
AST6
ABT6
Bit 5
0
0
AST5
ABT5
Bit 4
0
0
AST4
ABT4
Bit 3
0
0
AST3
ABT3
Bit 2
1
0
AST2
ABT2
Bit 1
1
0
AST1
ABT1
Bit 0
0
0
AST0
ABT0
A-WORD SEARCH TIME (AST)
The value of these bits sets the A-word search time for all asynchronous A-word
searches in units of 80 ms (e.g. value of 1 is 80 ms, value of 2 is 160 ms, etc.) If the
value is 0, FLEX chip defaults to the 1-minute (MOT = 1) or 4-minute (MOT = 0)
A-word search time controlled by the MOT bit in the configuration packet. The value
after reset = 0.
ASYNCHRONOUS BATTERY-SAVE TIME (ABT)
The value of these bits sets the battery save time (time from the beginning of one
automatic noise detect to the beginning of the next automatic noise detect) in
asynchronous mode in units of 80 ms (e.g. value of 1 is 80 ms, value of 2 is 160 ms,
etc.) If the value is 0, the battery save time is set to the default value of 1.5 seconds.
The minimum allowed ABT is 320 ms, therefore values of 1, 2, 3, and 4 are invalid.
The value after reset = 0.
Receiver Line Control Packet
This packet gives the host control over the settings on the receiver control lines
(S0–S7) in all modes except reset. In reset, the receiver control lines are in high
impedance settings. The ID for the Receiver Line Control Packet is 15 (decimal).
Table B-13 Receiver Line Control Packet Bit Assignments
Byte
3
2
1
0
Bit 7
0
0
FRS7
CLS7
Bit 6
0
0
FRS6
CLS6
Bit 5
0
0
FRS5
CLS5
Bit 4
0
0
FRS4
CLS4
Bit 3
1
0
FRS3
CLS3
Bit 2
1
0
FRS2
CLS2
Bit 1
1
0
FRS1
CLS1
Bit 0
1
0
FRS0
CLS0
B-18
MC68181 Technical Data Sheet
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