MC68181 Datasheet, PDF (110/119 Pages) Freescale Semiconductor, Inc – Advance Information ROAMING FLEX chip SIGNAL PROCESSOR

MC68181
Message Building
Freescale Semiconductor, Inc.
is not sent to the host. The first message is in phase A and has an address (WN 3),
vector (WN 7), and three message words (WN 9–11). The second message is also in
phase A and has an address (WN 4), a vector (WN 8), and four message words (WN
12–15). The third message is in phase C and has a 2 word long address (WN 5–6)
followed by a vector (WN 10) and three message words. Since the third message is
sent on a long address, the first message word (WN 11) begins immediately after the
vector. The vector indicates the location of the second and third message words (WN
14–15).
BLOCK
0
1
Word
Number
0
1
3
4
5
6
7
8
9
10
11
12
13
14
15
Table C-1 FLEX SIGNAL
PHASE A
PHASE C
BIW1
ADDRESS 1
ADDRESS 2
VECTOR 1
VECTOR 2
MESSAGE 1, 1
MESSAGE 1, 2
MESSAGE 1, 3
MESSAGE 2, 1
MESSAGE 2, 2
MESSAGE 2, 3
MESSAGE 2, 4
BIW1
BIW
BIW
LONG ADDRESS 3 WORD 1
LONG ADDRESS 3 WORD 2
VECTOR 3
MESSAGE 3, 1
MESSAGE 3, 2
MESSAGE 3, 3
Table C-2 on page C-7 shows the sequence of packets received by the host. The
FLEXchip processes the FLEX signal one block at a time, and one phase at a time.
Thus, the address and vector information in block 0 phase A is packetized and sent to
the host in packets 1–3. Then information in block 0 phase C, two block information
words and one long address, is packetized and sent to the host in packets 4–6. Packets
7–18 correspond to information in block 1, processed in phase A first and phase C
second.
C-6
MC68181 Technical Data Sheet
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