MC68181 Datasheet, PDF (111/119 Pages) Freescale Semiconductor, Inc – Advance Information ROAMING FLEX chip SIGNAL PROCESSOR

Freescale Semiconductor, Inc.
MC68181
Message Building
PACKET
1st
2nd
3rd
4th
5th
6th
7th
8th
9th
10th
11th
12th
13th
14th
15th
16th
17th
18th
Table C-2 FLEXchip PACKET SEQUENCE
PACKET
TYPE
PHASE
WORD
NUMBER
COMMENT
ADDRESS
A
N.A. (7) Address 1 has a vector located at WN 7.
ADDRESS
A
N.A. (8) Address 2 has a vector located at WN 8.
VECTOR
A
7
Vector for Address 1: Message Words
located at WN = 9 to 11, phase A
BIW
C
N.A.
If BIWs enabled, then BIW packet sent
BIW
C
N.A.
If BIWs enabled, then BIW packet sent
LONG
C
ADDRESS
N.A. (10)
Long Address 3 has a vector beginning in
word 10 of phase C.
VECTOR
A
8
Vector for Address 2: Message Words
located at WN = 12 to 15, phase A
MESSAGE
A
9
Message information for Address 1
MESSAGE
A
10
Message information for Address 1
MESSAGE
A
11
Message information for Address 1
MESSAGE
A
12
Message information for Address 2
MESSAGE
A
13
Message information for Address 2
MESSAGE
A
14
Message information for Address 2
MESSAGE
A
15
Message information for Address 2
VECTOR
C
10
Vector for Long Address 3: Message
Words located at WN = 14–15, phase C
MESSAGE
C
11
Second word of Long Vector is first
message information word of Address 3.
MESSAGE
C
14
Message information for Address 3
MESSAGE
C
15
Message information for Address 3
The first message is built by relating packets 1, 3, and 8–10. The second message is
built by relating packets 2, 7, and 11–14. The third message is built by relating packets
6 and 15–18. Additionally, the host may process block information in packets 4 and 5
for time setting information.
MOTOROLA
MC68181 Technical Data Sheet
C-7
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