MC9328MXL_06 Datasheet, PDF (75/90 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
Table 32. I²C Bus Timing Parameter Table
Ref No.
Parameter
1
Hold time (repeated) START condition
2
Data hold time
3
Data setup time
4
HIGH period of the SCL clock
5
LOW period of the SCL clock
6
Setup time for STOP condition
1.8 ± 0.1 V
3.0 ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
182
–
160
–
ns
0
171
0
150
ns
11.4
–
10
–
ns
80
–
120
–
ns
480
–
320
–
ns
182.4
–
160
–
ns
4.13 Synchronous Serial Interface
The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode,
the transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous
mode, the transmitter and receiver each have their own clock and frame synchronization signals.
Continuous or gated clock mode can be selected. In continuous mode, the clock runs continuously. In gated
clock mode, the clock functions only during transmission. The internal and external clock timing diagrams
are shown in Figure 60 through Figure 62.
Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of
I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is
typically used in star or ring-time division multiplex networks with other processors or codecs, allowing
interface to time division multiplexed networks without additional logic. Use of the gated clock is not
allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to
communicate with a wide variety of devices.
1
STCK Output
STFS (bl) Output
STFS (wl) Output
2
4
6
10
11
8
12
STXD Output
SRXD Input
31
32
Note: SRXD input in synchronous mode only.
Figure 59. SSI Transmitter Internal Clock Timing Diagram
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
75