MC9328MXL_06 Datasheet, PDF (56/90 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
Table 18. Timing Parameter Table for Figure 34 through Figure 38
Ref No.
Parameter
3.0 ± 0.3 V
Unit
Minimum
Maximum
1
SPI_RDY to SS output low
2T¹
–
ns
2
SS output low to first SCLK edge
3 • Tsclk²
–
ns
3
Last SCLK edge to SS output high
2 • Tsclk
–
ns
4
SS output high to SPI_RDY low
0
–
ns
5
SS output pulse width
Tsclk + WAIT ³
–
ns
6
SS input low to first SCLK edge
T
–
ns
7
SS input pulse width
T
–
ns
1 _{T = CSPI system clock period (PERCLK2).}
2 _{Tsclk = Period of SCLK.}
3 _{WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control Register.}
8
SCLK
9
9
Figure 39. SPI SCLK Timing Diagram
Table 19. Timing Parameter Table for SPI SCLK
Ref No.
Parameter
8
SCLK frequency
9
SCLK pulse width
3.0 ± 0.3 V
Minimum
Maximum
0
10
100
–
Unit
MHz
ns
4.6 LCD Controller
This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD
controller with various display configurations, refer to the LCD controller chapter of the MC9328MXL
Reference Manual.
LSCLK
1
LD[15:0]
Figure 40. SCLK to LD Timing Diagram
MC9328MXL Technical Data, Rev. 8
56
Freescale Semiconductor