MC9328MXL_06 Datasheet, PDF (29/90 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
Table 15. WAIT Write Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz (Continued)
Number
Characteristic
3.0 ± 0.3 V
Unit
Minimum
Maximum
7
Wait asserted to RW negated
T+2.66
2T+7.96
ns
8
Data hold timing after RW negated
2T+0.03
–
ns
9
Data ready after CS5 is asserted
–
T
ns
10
EB negated after CS5 is negated
0.5T
0.5T+0.5
ns
11
Wait becomes low after CS5 asserted
0
1019T
ns
12
Wait pulse width
1T
1020T
ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. CS5 assertion can be controlled by CSA bits. EB assertion can also be programmable by WEA bits in CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
4.4.2.4 WAIT Write Cycle DMA Enabled
Address
1
CS5
2
EB
RW
OE (logic high)
WAIT
DATABUS
3
programmable
min 0ns
programmable
min 0ns
5
10
11
7
4
6
12
9
8
13
Figure 9. WAIT Write Cycle DMA Enabled
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
29