MC9328MXL_06 Datasheet, PDF (21/90 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
Table 9. Trace Port Timing Diagram Parameter Table (Continued)
Ref No.
Parameter
4a Output hold time
4b Output setup time
1.8 ± 0.1 V
Minimum
Maximum
2.28
–
3.42
–
3.0 ± 0.3 V
Unit
Minimum
Maximum
2
–
ns
3
–
ns
4.2 DPLL Timing Specifications
Parameters of the DPLL are given in Table 10. In this table, T_ref is a reference clock period after the
pre-divider and T_dck is the output double clock period.
Table 10. DPLL Specifications
Parameter
Test Conditions
Minimum Typical Maximum Unit
DPLL input clock freq range Vcc = 1.8V
5
–
100
MHz
Pre-divider output clock
freq range
Vcc = 1.8V
5
–
30
MHz
DPLL output clock freq range Vcc = 1.8V
80
–
220
MHz
Pre-divider factor (PD)
–
1
–
16
–
Total multiplication factor (MF) Includes both integer and fractional parts
5
–
15
–
MF integer part
–
5
–
15
–
MF numerator
Should be less than the denominator
0
–
1022
–
MF denominator
–
1
–
1023
–
Pre-multiplier lock-in time
–
–
–
312.5
μsec
Freq lock-in time after
full reset
FOL mode for non-integer MF
(does not include pre-multi lock-in time)
250
280
(56 μs)
300
T_ref
Freq lock-in time after
partial reset
FOL mode for non-integer MF (does not
include pre-multi lock-in time)
220
250
(50 μs)
270
T_ref
Phase lock-in time after
full reset
FPL mode and integer MF (does not include
pre-multi lock-in time)
300
350
(70 μs)
400
T_ref
Phase lock-in time after
partial reset
FPL mode and integer MF (does not include
pre-multi lock-in time)
270
320
(64 μs)
370
T_ref
Freq jitter (p-p)
–
–
0.005
(0.01%)
0.01
2•T_dck
Phase jitter (p-p)
Integer MF, FPL mode, Vcc=1.8V
–
1.0
(10%)
1.5
ns
Power supply voltage
–
1.7
–
2.5
V
Power dissipation
FOL mode, integer MF,
f_dck = 200 MHz, Vcc = 1.8V
–
–
4
mW
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
21