MC9328MXL_06 Datasheet, PDF (22/90 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
4.3 Reset Module
The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and
Figure 4.
NOTE
Be aware that NVDD must ramp up to at least 1.8V before QVDD is powered up
to prevent forward biasing.
90% AVDD
1
POR
RESET_POR
RESET_DRAM
HRESET
RESET_OUT
CLK32
10% AVDD
2
Exact 300ms
3
7 cycles @ CLK32
4
14 cycles @ CLK32
HCLK
RESET_IN
HRESET
RESET_OUT
CLK32
HCLK
22
Figure 3. Timing Relationship with POR
5
14 cycles @ CLK32
4
6
Figure 4. Timing Relationship with RESET_IN
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor