MC9328MXL_06 Datasheet, PDF (68/90 Pages) Freescale Semiconductor, Inc – MX Family of applications processors

Functional Description and Application Information
Table 26. PWM Output Timing Parameter Table (Continued)
Ref No.
Parameter
3b Clock rise time¹
4a Output delay time¹
4b Output setup time¹
1 _{CL of PWMO = 30 pF}
1.8 ± 0.1 V
Minimum
Maximum
–
6.67
5.7
–
5.7
–
3.0 ± 0.3 V
Unit
Minimum
Maximum
–
5/10
ns
5
–
ns
5
–
ns
4.10 SDRAM Controller
This section shows timing diagrams and parameters associated with the SDRAM (synchronous dynamic
random access memory) Controller.
1
SDCLK
CS
2
3S
3
3S
RAS
CAS
WE
3H
3S
3H
3H
3S
3H
ADDR
DQ
DQM
4S 4H
ROW/BA
COL/BA
8
3S
5
6
Data
7
3H
Note: CKE is high during the read/write cycle.
Figure 52. SDRAM Read Cycle Timing Diagram
MC9328MXL Technical Data, Rev. 8
68
Freescale Semiconductor