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MC9328MXL_06 Datasheet, PDF (71/90 Pages) Freescale Semiconductor, Inc – MX Family of applications processors | |||
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SDCLK
CS
13
2
Functional Description and Application Information
RAS
6
CAS
WE
ADDR
4
5
BA
7
7
ROW/BA
DQ
DQM
Figure 54. SDRAM Refresh Timing Diagram
Table 29. SDRAM Refresh Timing Parameter Table
Ref No.
Parameter
1.8 ± 0.1 V
3.0 ± 0.3 V
Unit
Minimum
Maximum
Minimum
Maximum
1 SDRAM clock high-level width
2.67
â
4
â
ns
2 SDRAM clock low-level width
6
â
4
â
ns
3 SDRAM clock cycle time
11.4
â
10
â
ns
4 Address setup time
3.42
â
3
â
ns
5 Address hold time
2.28
â
2
â
ns
6 Precharge cycle period
tRP1
â
tRP1
â
ns
7 Auto precharge command period
tRC1
â
tRC1
â
ns
1 tRP and tRC = SDRAM clock cycle time. These settings can be found in the MC9328MXL reference manual.
MC9328MXL Technical Data, Rev. 8
Freescale Semiconductor
71
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