MC9S12E64CFUE Datasheet, PDF (74/606 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1)
1.5 System Clock Description
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 1-10 shows the clock connections from the CRG to all modules. Consult the CRG block description
chapter for details on clock generation.
Core Clock
HCS12 CORE
BDM CPU
MEBI MMC
INT DBG
EXTAL
XTAL
OSC
CRG
Bus Clock
Oscillator Clock
Figure 1-10. Clock Connections
Flash
RAM
ATD
DAC
IIC
PIM
PMF
PWM
SCI0, SCI1, SCI2
SPI
TIM0, TIM1, TIM2
VREG
Table 1-6. Clock Selection Based on PE7
PE7 = XCLKS
Description
1
Colpitts Oscillator selected
0
Pierce Oscillator/external clock selected
MC9S12E128 Data Sheet, Rev. 1.07
74
Freescale Semiconductor