MC9S12E64CFUE Datasheet, PDF (138/606 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 3 Port Integration Module (PIM9E128V1)
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
3.3.2.3 Port M Data Direction Register (DDRM)
7
6
5
4
3
2
1
0
R
0
DDRM7
DDRM6
DDRM5
DDRM4
DDRM3
DDRM1
DDRM0
W
Reset
0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 3-12. Port M Data Direction Register (DDRM)
Read: Anytime. Write: Anytime.
This register configures port pins PM[7:3] and PM[1:0] as either input or output.
If the IIC is enabled, the IIC controls the SCL and SDA I/O direction, and the corresponding DDRM[7:6]
bits have no effect on their I/O direction. Refer to the IIC block description chapter for details.
If the SCI2 transmitter is enabled, the I/O direction of the transmit pin TXD2 is controlled by SCI2, and
the DDRM5 bit has no effect. If the SCI2 receiver is enabled, the I/O direction of the receive pin RXD2 is
controlled by SCI2, and the DDRM4 bit has no effect. Refer to the SCI block description chapter for
further details.
If the DAC1 or DAC0 channel is enabled, the associated pin DAO1 or DAO0 is forced to be output, and
the associated DDRM1 or DDRM0 bit has no effect.
The DDRM bits do not change to reflect the pin I/O direction when not being used as GPIO. The
DDRM[7:3]; DDRM[1:0] bits revert to controlling the I/O direction of the pins when the associated IIC,
SCI, or DAC1/0 function are disabled.
Table 3-9. DDRM Field Descriptions
Field
7:3, 1:0 Data Direction Port M
DDRM[7:3, 0 Associated pin is configured as input.
1:0]
1 Associated pin is configured as output.
Description
MC9S12E128 Data Sheet, Rev. 1.07
138
Freescale Semiconductor