MC9S12E64CFUE Datasheet, PDF (156/606 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 3 Port Integration Module (PIM9E128V1)
3.3.7.3 Port U Data Direction Register (DDRU)
R
W
Reset
7
DDRU7
0
6
DDRU6
5
DDRU5
4
DDRU4
3
DDRU3
2
DDRU2
0
0
0
0
0
Figure 3-44. Port U Data Direction Register (DDRU)
1
DDRU1
0
0
DDRU0
0
Read: Anytime. Write: Anytime.
This register configures port pins PU[7:0] as either input or output.
If a pulse width modulator channel is enabled, the associated pin is forced to be an output and the
associated Data Direction Register bit has no effect. If the associated pulse width modulator channel is
disabled, the corresponding DDRUx bit reverts to control the I/O direction of the associated pin.
If the TIM2 module is enabled, each port pin configured for output compare is forced to be an output and
the associated Data Direction Register bit has no effect. If the associated timer output compare is disabled,
the corresponding DDRUx bit reverts to control the I/O direction of the associated pin.
If the TIM2 module is enabled, each port pin configured as an input capture has the corresponding DDRUx
bit controlling the I/O direction of the associated pin.
When both a timer function and a PWM function are enabled on the same pin, the MODRR register
determines which function has control of the pin
Table 3-31. DDRT Field Descriptions
Field
7:0
Data Direction Port U
DDRU[7:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
MC9S12E128 Data Sheet, Rev. 1.07
156
Freescale Semiconductor