MC9S12E64CFUE Datasheet, PDF (337/606 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
Table 11-10. Qualifying Samples
QSMPx
Number of Samples
00
1 sample¹
01
5 samples
10
10 samples
11
15 samples
1 _{There is an asynchronous path from fault pin to disable}
PWMs immediately but the fault is qualified in two bus
cycles.
11.3.2.9 PMF Disable Mapping Registers
Module Base + 0x0008
R
W
Reset
7
DMP13
0
6
DMP12
5
DMP11
4
DMP10
3
DMP03
2
DMP02
1
DMP01
0
0
0
0
0
0
Figure 11-12. PMF Disable Mapping A Register (PMFDMPA)
0
DMP00
0
Module Base + 0x0009
R
W
Reset
7
DMP33
0
6
DMP32
5
DMP31
4
DMP30
3
DMP23
2
DMP22
1
DMP21
0
0
0
0
0
0
Figure 11-13. PMF Disable Mapping B Register (PMFDMPB)
0
DMP20
0
Module Base + 0x000A
R
W
Reset
7
DMP53
0
6
DMP52
5
DMP51
4
DMP50
3
DMP43
2
DMP42
1
DMP41
0
0
0
0
0
0
Figure 11-14. PMF Disable Mapping C Register (PMFDMPC)
Read anytime. These registers cannot be modified after the WP bit is set.
0
DMP40
0
Table 11-11. PMFDMPA, PMFDMPB, and PMFDMPC Field Descriptions
Field
Description
7–0
PMF Disable Mapping Bits — The fault decoder disables PWM pins selected by the fault logic and the disable
DMP[00:53] mapping registers. See Figure 11-15. Each bank of four bits in the disable mapping registers control the mapping
of a single PWM pin. Refer to Table 11-12.
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor
337