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MC9S12E64CFUE Datasheet, PDF (586/606 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Appendix A Electrical Characteristics
In Figure A-5 the timing diagram for master mode with transmission format CPHA=1 is depicted.
SS1
(OUTPUT)
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
MISO
(INPUT)
1
2
4
4
5
6
MSB IN2
9
MOSI
(OUTPUT)
PORT DATA
MASTER MSB OUT2
12
12
BIT 6 . . . 1
11
BIT 6 . . . 1
13
3
13
LSB IN
MASTER LSB OUT
PORT DATA
1.If conï¬gured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure A-5. SPI Master Timing (CPHA=1)
In Table A-17 the timing characteristics for master mode are listed.
Table A-17. SPI Master Mode Timing Characteristics
Num
1
1
2
3
4
5
6
9
10
11
12
13
C
Characteristic
P SCK Frequency
P SCK Period
D Enable Lead Time
D Enable Lag Time
D Clock (SCK) High or Low Time
D Data Setup Time (Inputs)
D Data Hold Time (Inputs)
D Data Valid after SCK Edge
D Data Valid after SS fall (CPHA = 0)
D Data Hold Time (Outputs)
D Rise and Fall Time Inputs
D Rise and Fall Time Outputs
Symbol
Min
Typ
fsck
1/2048
â
tsck
2
â
tlead
â
1/2
tlag
â
1/2
twsck
â
1/2
tsu
8
â
thi
8
â
tvsck
â
â
tvss
â
â
tho
20
â
trï¬
â
â
trfo
â
â
Max
1/2
2048
â
â
â
â
â
30
15
â
8
8
Unit
fbus
tbus
tsck
tsck
tsck
ns
ns
ns
ns
ns
ns
ns
MC9S12E128 Data Sheet, Rev. 1.07
586
Freescale Semiconductor
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