MC9S12E64CFUE Datasheet, PDF (153/606 Pages) Freescale Semiconductor, Inc – Microcontrollers

3.3.6.3
Port T Data Direction Register (DDRT)
Chapter 3 Port Integration Module (PIM9E128V1)
R
W
Reset
7
DDRT7
0
6
DDRT6
5
DDRT5
4
DDRT4
3
DDRT3
2
DDRT2
0
0
0
0
0
Figure 3-38. Port T Data Direction Register (DDRT)
1
DDRT1
0
0
DDRT0
0
Read: Anytime. Write: Anytime.
This register configures port pins PT[7:0] as either input or output.
If the TIM0(1) module is enabled, each port pin configured for output compare is forced to be an output
and the associated Data Direction Register bit has no effect. If the associated timer output compare is
disabled, the corresponding DDRTx bit reverts to control the I/O direction of the associated pin.
If the TIM0(1) module is enabled, each port pin configured as an input capture has the corresponding
DDRTx bit controlling the I/O direction of the associated pin.
Table 3-27. DDRT Field Descriptions
Field
7:0
Data Direction Port T
DDRT[7:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
3.3.6.4 Port T Reduced Drive Register (RDRT)
R
W
Reset
7
RDRT7
0
6
RDRT6
5
RDRT5
4
RDRT4
3
RDRT3
2
RDRT2
0
0
0
0
0
Figure 3-39. Port T Reduced Drive Register (RDRT)
1
RDRT1
0
0
RDRT0
0
Read: Anytime. Write: Anytime.
This register configures the drive strength of configured output pins as either full or reduced. If a pin is
configured as input, the corresponding Reduced Drive Register bit has no effect.
Table 3-28. RDRT Field Descriptions
Field
Description
7:0
Reduced Drive Port T
RDRT[7:0] 0 Full drive strength at output.
1 Associated pin drives at about 1/3 of the full drive strength.
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor
153