MC9S12E128 Datasheet, PDF (63/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 1 MC9S12E128 Device Overview (MC9S12E128DGV1)
Table 1-4. Signal Properties
Pin Name Pin Name
Function 1 Function 2
Pin Name Power
Function 3 Domain
Internal Pull Resistor
CTRL Reset State
Description
PM0
DAO0
—
VDDX PERM/
Disabled Port M I/O Pin, DAC0 output
PPSM
PP[5:0]
PW0[5:0]
—
VDDX PERP/
Disabled Port P I/O Pins, PWM output
PPSP
PQ[6:4]
IS[6:4]
—
VDDX PERQ/
Disabled Port Q I/O Pins, IS[6:4] input
PPSQ
PQ[3:0]
FAULT[3:0]
—
VDDX PERQ/
Disabled Port Q I/O Pins, Fault[3:0] input
PPSQ
PS7
SS
—
VDDX PERS/
PPSS
Up
Port S I/O Pin, SPI SS signal
PS6
SCK
—
VDDX PERS/
PPSS
Up
Port S I/O Pin, SPI SCK signal
PS5
MOSI
—
VDDX PERS/
PPSS
Up
Port S I/O Pin, SPI MOSI signal
PS4
MISO
—
VDDX PERS/
PPSS
Up
Port S I/O Pin, SPI MISO signal
PS3
TXD1
—
VDDX PERS/
PPSS
Up
Port S I/O Pin, SCI1 transmit signal
PS2
RXD1
—
VDDX PERS/
PPSS
Up
Port S I/O Pin, SCI1 receive signal
PS1
TXD0
—
VDDX PERS/
PPSS
Up
Port S I/O Pin, SCI0 transmit signal
PS0
RXD0
—
VDDX PERS/
PPSS
Up
Port S I/O Pin, SCI0 receive signal
PT[7:4]
IOC1[7:4]
—
VDDX PERT/
Disabled Port T I/O Pins, timer (TIM1)
PPST
PT[3:0]
IOC0[7:4]
—
VDDX PERT/
Disabled Port T I/O Pins, timer (TIM0)
PPST
PU[7:6]
—
—
VDDX PERU/
Disabled Port U I/O Pins
PPSU
PU[5:4]
PW1[5:4]
—
VDDX PERU/
Disabled Port U I/O Pins, PWM outputs
PPSU
PU[3:0]
IOC2[7:4]
PW1[3:0]
VDDX
PERU/
PPSU
Disabled Port U I/O Pins, timer (TIM2), PWM
outputs
1 _{The Port E output buffer enable signal control at reset is determined by the PEAR register and is mode dependent. For}
example, in special test mode RDWE = LSTRE = 1 which enables the PE[3:2] output buffers and disables the pull-ups. Refer
to the S12 MEBI block description chapter for PEAR register details.
NOTE
Signals shown in bold are not available in the 112-pin package.
Signals shown in italic are not available in the 80-pin package.
If the port pins are not bonded out in the chosen package the user should initialize the registers to be inputs
with enabled pull resistance to avoid excess current consumption. This applies to the following pins:
(80QFP): Port A[7:0], Port B[7:0], Port E[6,5,3,2], Port K[7:0], Port U[7:4]
(64QFN): Port U[3:0], Port Q[6:4], Port M[3], Port AD[14,11,10,9,7,5,3,1]
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor
63