MC9S12E128 Datasheet, PDF (128/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 3 Port Integration Module (PIM9E128V1)
Address Offset
0x0020
0x0021
0x0022
0x0023
0x0024
0x0025
0x0026 - 0x0027
0x0028
0x0029
0x002A
0x002B
0x002C
0x002D
0x002E
0x002F
0x0030
0x0031
0x0032
0x0033
0x0034
0x0035
0x0036
0x0037
0x0038
0x0039
0x003A
0x003B
0x003D
0x003D
0x003E
0x003F
Table 3-2. PIM9HZ256 Memory Map (continued)
Use
Port Q I/O Register (PTQ)
Port Q Input Register (PTIQ)
Port Q Data Direction Register (DDRQ)
Port Q Reduced Drive Register (RDRQ)
Port Q Pull Device Enable Register (PERQ)
Port Q Polarity Select Register (PPSQ)
Reserved
Port U I/O Register (PTU)
Port U Input Register (PTIU)
Port U Data Direction Register (DDRU)
Port U Reduced Drive Register (RDRU)
Port U Pull Device Enable Register (PERU)
Port U Polarity Select Register (PPSU)
Port U Module Routing Register (MODRR)
Reserved
Port AD I/O Register (PTAD)
Port AD Input Register (PTIAD)
Port AD Data Direction Register (DDRAD)
Port AD Reduced Drive Register (RDRAD)
Port AD Pull Device Enable Register (PERAD)
Port AD Polarity Select Register (PPSAD)
Port AD Interrupt Enable Register (PIEAD)
Port AD Interrupt Flag Register (PIFAD)
Access
R/W
R
R/W
R/W
R/W
R/W
—
R/W
R
R/W
R/W
R/W
R/W
R/W
—
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
3.3.1 Port AD
Port AD is associated with the analog-to-digital converter (ATD) and keyboard wake-up (KWU)
interrupts. Each pin is assigned to these modules according to the following priority: ATD > KWU >
general-purpose I/O.
For the pins of port AD to be used as inputs, the corresponding bits of the ATDDIEN0 and ATDDIEN1
registers in the ATD module must be set to 1 (digital input buffer is enabled). The ATDDIEN0 and
ATDDIEN1 registers do not affect the port AD pins when they are configured as outputs.
MC9S12E128 Data Sheet, Rev. 1.07
128
Freescale Semiconductor