MC9S12E128 Datasheet, PDF (369/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
NOTE
Values latched on the ISx pins are buffered so only one PWM register is
used per PWM cycle. If a current status changes during a PWM period, the
new value does not take effect until the next PWM period.
When initially enabled by setting the PWMEN bit, no current status has previously been sampled. PWM
value registers one, three, and five initially control the three PWM pairs when configured for current status
correction.
11.4.5.4 Output Polarity
Output polarity of the PWMs is determined by two options: TOPNEG and BOTNEG. The top polarity
option, TOPNEG, controls the polarity of PWM0, PWM2 and PWM4. The bottom polarity option,
BOTNEG, controls the polarity of PWM1, PWM3 and PWM5. Positive polarity means when the PWM is
active its output is high. Conversely, negative polarity means when the PWM is active its output is low.
The TOPNEG and BOTNEG are in the configure register. TOPNEG is the output of PWM0, PWM2 and
PWM4. They are active low. If TOPNEG is set, PWM0, PWM2, and PWM4 outputs become active-low.
When BOTNEG is set, PWM1, PWM3, and PWM5 outputs are active-low. When these bits are clear, their
respective PWM pins are active-high. See Figure 11-59 and Figure 11-60.
DESIRED LOAD VOLTAGE
TOP PWM
BOTTOM PWM
LOAD VOLTAGE
Figure 11-59. Correction with Positive Current
DESIRED LOAD VOLTAGE
TOP PWM
BOTTOM PWM
LOAD VOLTAGE
Figure 11-60. Correction with Negative Current
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor
369