MC9S12E128 Datasheet, PDF (430/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 13 Timer Module (TIM16B4CV1)
13.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
TOF
W
Reset
0
0
0
0
0
0
0
0
Unimplemented or Reserved
Figure 13-19. Main Timer Interrupt Flag 2 (TFLG2)
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit
to one.
Read: Anytime
Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared).
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.
Table 13-16. TRLG2 Field Descriptions
Field
7
TOF
Description
Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. This bit is cleared
automatically by a write to the TFLG2 register with bit 7 set. (See also TCRE control bit explanation.)
13.3.2.14 Timer Input Capture/Output Compare Registers High and Low 4–7
(TCxH and TCxL)
15
R
Bit 15
W
14
Bit 14
11
Bit 13
12
Bit 12
11
Bit 11
10
Bit 10
9
Bit 9
0
Bit 8
Reset
0
0
0
0
0
0
0
0
Figure 13-20. Timer Input Capture/Output Compare Register x High (TCxH)
7
R
Bit 7
W
6
Bit 6
5
Bit 5
4
Bit 4
3
Bit 3
2
Bit 2
1
Bit 1
0
Bit 0
Reset
0
0
0
0
0
0
0
0
Figure 13-21. Timer Input Capture/Output Compare Register x Low (TCxL)
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the
free-running counter when a defined transition is sensed by the corresponding input capture edge detector
or to trigger an output action for output compare.
Read: Anytime
MC9S12E128 Data Sheet, Rev. 1.07
430
Freescale Semiconductor