|
MC9S12E128 Datasheet, PDF (507/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers | |||
|
◁ |
Chapter 17 Interrupt (INTV1)
17.2 External Signal Description
Most interfacing with the interrupt sub-block is done within the core. However, the interrupt does receive
direct input from the multiplexed external bus interface (MEBI) sub-block of the core for the IRQ and
XIRQ pin data.
17.3 Memory Map and Register Deï¬nition
Detailed descriptions of the registers and associated bits are given in the subsections that follow.
17.3.1 Module Memory Map
Table 17-1. INT Memory Map
Address
Offset
0x0015
0x0016
0x001F
Use
Interrupt Test Control Register (ITCR)
Interrupt Test Registers (ITEST)
Highest Priority Interrupt (Optional) (HPRIO)
17.3.2 Register Descriptions
Access
R/W
R/W
R/W
17.3.2.1 Interrupt Test Control Register
7
6
5
4
3
2
R
0
0
0
WRTINT
ADR3
ADR2
W
Reset
0
0
0
0
1
1
= Unimplemented or Reserved
Figure 17-2. Interrupt Test Control Register (ITCR)
Read: See individual bit descriptions
Write: See individual bit descriptions
1
ADR1
1
0
ADR0
1
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor
507
|
▷ |