PXN20 Datasheet, PDF (56/60 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Electrical characteristics
M3
M4
RX_CLK (input)
RXD[3:0] (inputs)
RX_DV
RX_ER
M1
M2
Figure 24. MII receive signal timing diagram
4.14.7.2 MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)
The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. In addition, the system clock frequency must exceed four times the TX_CLK frequency.
The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of
TX_CLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs.
Refer to the Ethernet chapter for details of this option and how to enable it.
Table 34. MII transmit signal timing¹
Spec
Characteristic
M5 TX_CLK to TXD[3:0], TX_EN, TX_ER invalid
M6 TX_CLK to TXD[3:0], TX_EN, TX_ER valid
M7 TX_CLK pulse width high
M8 TX_CLK pulse width low
1 _{Output pads configured with SRC = 0b11.}
Min
5
—
35%
35%
Max
—
25
65%
65%
Unit
ns
ns
TX_CLK period
TX_CLK period
M7
TX_CLK (input)
TXD[3:0] (outputs)
TX_EN
TX_ER
M5
M8
M6
Figure 25. MII transmit signal timing diagram
4.14.7.3 MII async inputs signal timing (CRS and COL)
Table 35. MII Async Inputs Signal Timing¹
Spec
Characteristic
Min
M9 CRS, COL minimum pulse width
1.5
1 _{Output pads configured with SRC = 0b11.}
PXN20 Microcontroller Data Sheet, Rev. 1
56
Max
Unit
—
TX_CLK period
Freescale Semiconductor