PXN20 Datasheet, PDF (44/60 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Electrical characteristics
4.14.3 JTAG (IEEE 1149.1) interface
Table 27. JTAG interface timing¹
Spec
Characteristic
Symbol
Min
Max Unit
1 TCK Cycle Time
t_JCYC
100
—
ns
2 TCK Clock Pulse Width (Measured at V_DDE/2)
t_JDC
40
60
ns
3 TCK Rise and Fall Times (40% – 70%)
t_TCKRISE
—
3
ns
4 TMS, TDI Data Setup Time
t_TMSS, t_TDIS
5
—
ns
5 TMS, TDI Data Hold Time
t_TMSH, t_TDIH
25
—
ns
6 TCK Low to TDO Data Valid
t_TDOV
—
25
ns
7 TCK Low to TDO Data Invalid
t_TDOI
0
—
ns
8 TCK Low to TDO High Impedance
t_TDOHZ
—
20
ns
9 JCOMP Assertion Time
t_JCMPPW
100
—
ns
10 JCOMP Setup Time to TCK Low
t_JCMPS
40
—
ns
11 TCK Falling Edge to Output Valid
t_BSDV
—
50
ns
12 TCK Falling Edge to Output Valid out of High Impedance
t_BSDVZ
—
50
ns
13 TCK Falling Edge to Output High Impedance
t_BSDHZ
—
50
ns
14 Boundary Scan Input Valid to TCK Rising Edge
t_BSDST
50
—
ns
15 TCK Rising Edge to Boundary Scan Input Invalid
t_BSDHT
50
—
ns
1 _{These specifications apply to JTAG boundary scan only. JTAG timing specified at VDDE = 3.0 – 5.5 V, TA = TL to TH, and}
C_L = 30 pF with SRC = 0b11.
TCK
3
2
2
1
3
Figure 9. JTAG test clock input timing
PXN20 Microcontroller Data Sheet, Rev. 1
44
Freescale Semiconductor