PXN20 Datasheet, PDF (55/60 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Electrical characteristics
1 _{The Controller can shut off MLBCLK to place MLB in a low-power state.}
2 _{Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other}
edge, measured in ns peak-to-peak (ns p-p).
3 _{The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this}
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
MLBSIG/
MLBDAT
(input)
2
MLBCLK
MLBSIG/
MLBDAT
(output)
valid data
8
6
4
12
10
valid data
9
3
5
11
Figure 23. Media Local Bus (MLB) timing
4.14.7 Fast Ethernet Controller (FEC) interface
MII signals use CMOS signal levels compatible with devices operating at either 5.0 V or 3.3 V. Signals are not TTL compatible.
They follow the CMOS electrical characteristics.
4.14.7.1 MII receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. In addition, the system clock frequency must exceed four times the RX_CLK frequency.
Table 33. MII receive signal timing
Spec
Characteristic
Min
Max
Unit
M1 RXD[3:0], RX_DV, RX_ER to RX_CLK setup
M2 RX_CLK to RXD[3:0], RX_DV, RX_ER hold
M3 RX_CLK pulse width high
M4 RX_CLK pulse width low
5
5
35%
35%
—
—
65%
65%
ns
ns
RX_CLK period
RX_CLK period
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
55