PXN20 Datasheet, PDF (48/60 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Electrical characteristics
4.14.5 Deserial Serial Peripheral Interface (DSPI)
Table 29. DSPI timing
Spec
Characteristic
Symbol
116 MHz¹
Unit
Min. Value Max. Value
1 DSPI Cycle Time
Master (MTFE = 0)
Slave (MTFE = 0)
Master (MTFE = 1)
Slave (MTFE = 1)
2
PCS to SCK Delay²
3
After SCK Delay³
4 SCK Duty Cycle
5 Slave Access Time
(SS active to SOUT valid)
t_SCK
t_CSC
t_ASC
t_SDC
t_A
100
—
ns
100
—
ns
50
—
ns
50
—
ns
7
—
ns
14
—
ns
0.4  t_SCK
0.6  t_SCK
ns
—
25
ns
6 Slave SOUT Disable Time
(SS inactive to SOUT High-Z or invalid)
t_DIS
—
25
ns
7 PCSx to PCSS time
8 PCSS to PCSx time
9 Data Setup Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)⁴
Master (MTFE = 1, CPHA = 1)
t_PCSC
0
t_PASC
0
t_SUI
25
5
10
25
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
10 Data Hold Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)⁴
Master (MTFE = 1, CPHA = 1)
t_HI
–4
7
12
–4
—
ns
—
ns
—
ns
—
ns
11 Data Valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
t_SUO
—
—
—
—
8
ns
28
ns
15
ns
8
ns
12 Data Hold Time for Outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
t_HO
–7
2
1
–7
1 _{116 MHz timing specified at CL = 50 pF with SRC = 0b11.}
2 _{The maximum value is programmable in DSPI_CTARn[PSSCK] and DSPI_CTARn[CSSCK].}
3 _{The maximum value is programmable in DSPI_CTARn[PASC] and DSPI_CTARn[ASC].}
4 _{This number is calculated assuming the SMPL_PT bit field in DSPI_MCR is set to 0b10.}
—
ns
—
ns
—
ns
—
ns
PXN20 Microcontroller Data Sheet, Rev. 1
48
Freescale Semiconductor