PXN20 Datasheet, PDF (23/60 Pages) Freescale Semiconductor, Inc – PXN20 Microcontroller

Pin assignments
Table 3. PXN20 signal properties (continued)
Pin
Name¹
Supported
Functions²
GPIO
(PCR) PA⁴
Num³
Description
I/O
Type
Volt-
age
Status
Pad
Type⁵ _During
Reset⁶
After
Reset⁷
Package Pin
Locations
208
BGA
PK6 PK[6]
150 00 Port K GPIO
FR_B_RX
01 FlexRay B Receive Data
I/O V_DDE2 SH
—
—
R5
I
PCS_B[1]
10 DSPI_B Peripheral Chip Select O
PCS_C[4]
11 DSPI_C Peripheral Chip Select O
PK7 PK[7]
151 00 Port K GPIO
FR_B_TX
01 FlexRay B Transmit Data
I/O V_DDE2 MH —
—
T5
O
PCS_B[2]
10 DSPI_B Peripheral Chip Select O
PCS_C[5]
11 DSPI_C Peripheral Chip Select O
PK8 PK[8]
152 00 Port K GPIO
I/O V_DDE2 MH —
—
R6
FR_B_TX_EN
01 FlexRay B Transmit Enable
O
PCS_B[3]
10 DSPI_B Peripheral Chip Select O
PCS_A[1]
11 DSPI_A Peripheral Chip Select O
PK9 PK[9]
CLKOUT
153 00 Port K GPIO
01 CLKOUT (User mode)
I/O V_DDE2 MH BOOT GPIO
T6
O
CFG
PCS_D[1]
10 DSPI_D Peripheral Chip Select O
(Pull-
PCS_A[2]
11 DSPI_A Peripheral Chip Select O
down)
BOOTCFG
Boot Configuration
I
PK10 PK[10]
154 00 Port K GPIO
I/O V_DDE2 SH
—
—
P6
PCS_B[5]
01 DSPI_B Peripheral Chip Select O
PCS_D[2]
10 DSPI_D Peripheral Chip Select O
PCS_A[3]
11 DSPI_A Peripheral Chip Select O
Miscellaneous Pins (9)
EXTAL EXTAL
— — Main Crystal Oscillator Input
I V_DDSYN A
EXTAL
A14
EXTCLK
External Clock Input
I
XTAL XTAL
— — Main Crystal Oscillator Output
O V_DDSYN A
XTAL
A13
TDI
TDO
TDI
TDO
— — JTAG Test Data Input
— — JTAG Test Data Output
I V_DDE2 SH TDI (Pull Up)
J3
O V_DDE2 MH TDO (Pull Up⁸)
M3
TMS TMS
— — JTAG Test Mode Select Input
I V_DDE2 MH TMS (Pull Up)
L3
TCK TCK
— — JTAG Test Clock Input
I V_DDE2 SH TCK (Pull Down)
P3
JCOMP JCOMP
TEST TEST
— — JTAG Compliancy
— — Test Mode Select
I V_DDE2 SH JCOMP (Pull Down)
I V_DDE3 IH
TEST⁹
K3
M13
RESET RESET
— — External Reset
I/O V_DDE1 MH RESET (Pull Up)
A11
1 _{The primary signal name is used as the pin label on the BGA map for identification purposes.}
2 _{Each line in the Signal Name column corresponds to a separate signal function on the pin. For all device I/O pins, the primary,}
alternate, or GPIO signal functions are designated in the PA field of the System Integration Unit (SIU) PCR registers except
where explicitly noted.
3 _{The GPIO number is the same as the corresponding pad configuration register (SIU_PCRn) number.}
4 _{The PA bitfield in the SIU_PCRn register selects the signal function for the pin. A dash in the Description field of this table}
indicates that this value for PC is reserved on this pin, and should not be used.
PXN20 Microcontroller Data Sheet, Rev. 1
Freescale Semiconductor
23