K11P121M50SF4 Datasheet, PDF (55/59 Pages) Freescale Semiconductor, Inc – K11 Sub-Family Data Sheet

121 Default
MAP
BGA
B11 DISABLED
C11 DISABLED
B10 DISABLED
E9 DISABLED
D9 DISABLED
C9 DISABLED
B9 ADC0_SE14
D8 ADC0_SE15
C8 ADC0_SE4b/
CMP1_IN0
B8 CMP1_IN1
G3 VSS
E5 VDD
A8 DISABLED
D7 DISABLED
C7 CMP0_IN0
B7 CMP0_IN1
A7 CMP0_IN2
D6 CMP0_IN3
C6 DISABLED
C5 DISABLED
B6 DISABLED
A6 DISABLED
D5 DISABLED
C4 DISABLED
D4 DISABLED
D3 ADC0_SE5b
C3 DISABLED
B3 DISABLED
A3 ADC0_SE21
A2 ADC0_SE6b
ALT0
ADC0_SE14
ADC0_SE15
ADC0_SE4b/
CMP1_IN0
CMP1_IN1
VSS
VDD
CMP0_IN0
CMP0_IN1
CMP0_IN2
CMP0_IN3
ADC0_SE5b
ADC0_SE21
ADC0_SE6b
ALT1
PTB12
PTB13
PTB16
PTB17
PTB18
PTB19
PTC0
PTC1/
LLWU_P6
PTC2
PTC3/
LLWU_P7
PTC4/
LLWU_P8
PTC5/
LLWU_P9
PTC6/
LLWU_P10
PTC7
PTC8
PTC9
PTC10
PTC11/
LLWU_P11
PTC12
PTC13
PTC16
PTC17
PTD0/
LLWU_P12
PTD1
PTD2/
LLWU_P13
PTD3
PTD4/
LLWU_P14
PTD5
B2 ADC0_SE7b
A1 ADC0_SE22
ADC0_SE7b
ADC0_SE22
PTD6/
LLWU_P15
PTD7
ALT2
ALT3
ALT4
UART3_RTS_b
UART3_CTS_b
SPI1_SOUT
SPI1_SIN
SPI0_PCS4
SPI0_PCS3
FTM1_CH0
FTM1_CH1
UART0_RX
UART0_TX
FTM2_CH0
FTM2_CH1
PDB0_EXTRG
UART1_RTS_b
FTM0_CH4
FTM0_CH5
I2S0_TX_BCLK
I2S0_TX_FS
FTM0_CH0
SPI0_PCS2 UART1_CTS_b FTM0_CH1
SPI0_PCS1 UART1_RX FTM0_CH2
SPI0_PCS0 UART1_TX FTM0_CH3
SPI0_SCK
LPTMR0_ALT2 I2S0_RXD0
SPI0_SOUT PDB0_EXTRG I2S0_RX_BCLK
SPI0_SIN
I2C1_SCL
I2C1_SDA
I2S0_RX_FS
I2S0_MCLK
I2S0_RX_BCLK
I2S0_RX_FS
I2S0_RXD1
SPI0_PCS0
UART3_RX
UART3_TX
UART2_RTS_b
SPI0_SCK
SPI0_SOUT
UART2_CTS_b
UART2_RX I2C0_SCL
SPI0_SIN
SPI0_PCS1
UART2_TX I2C0_SDA
UART0_RTS_b FTM0_CH4
SPI0_PCS2
SPI0_PCS3
UART0_CTS_b/
UART0_COL_b
UART0_RX
FTM0_CH5
FTM0_CH6
CMT_IRO
UART0_TX FTM0_CH7
ALT5
ALT6
ALT7
FTM1_QD_PHA
FTM1_QD_PHB
EWM_IN
EWM_OUT_b
FTM2_QD_PHA
FTM2_QD_PHB
I2S0_TXD1
I2S0_TXD0
FTM_CLKIN0
FTM_CLKIN1
I2S0_TX_FS
I2S0_TX_BCLK
CMP1_OUT
CMP0_OUT
I2S0_MCLK
FTM0_CH2
FTM2_FLT0
EWM_IN
EWM_OUT_b
FTM0_FLT0
FTM0_FLT1
K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.
Freescale Semiconductor, Inc.
Pinout
EzPort
55