K11P121M50SF4 Datasheet, PDF (22/59 Pages) Freescale Semiconductor, Inc – K11 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
Table 13. JTAG full voltage range electricals
Symbol
J1
Description
Operating voltage
TCLK frequency of operation
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
Min.
1.71
0
0
0
J2
TCLK cycle period
1/J1
J3
TCLK clock pulse width
• Boundary Scan
50
• JTAG and CJTAG
25
• Serial Wire Debug
12.5
J4
TCLK rise and fall times
—
J5
Boundary scan input data setup time to TCLK rise
20
J6
Boundary scan input data hold time after TCLK rise
0
J7
TCLK low to boundary scan output data valid
—
J8
TCLK low to boundary scan output high-Z
—
J9
TMS, TDI input data setup time to TCLK rise
8
J10
TMS, TDI input data hold time after TCLK rise
1.4
J11
TCLK low to TDO data valid
—
J12
TCLK low to TDO high-Z
—
J13
TRST assert time
100
J14
TRST setup time (negation) to TCLK high
8
Max.
3.6
10
20
40
—
—
—
—
3
—
—
25
25
—
—
22.1
22.1
—
—
TCLK (input)
J2
J3
J3
J4
J4
Figure 4. Test clock input timing
Unit
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.
22
Freescale Semiconductor, Inc.