K11P121M50SF4 Datasheet, PDF (38/59 Pages) Freescale Semiconductor, Inc – K11 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
6.6.2 CMP and 6-bit DAC electrical specifications
Table 26. Comparator and 6-bit DAC electrical specifications
Symbol
V_DD
I_DDHS
I_DDLS
V_AIN
V_AIO
V_H
Description
Supply voltage
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
Analog input offset voltage
Analog comparator hysteresis¹
• CR0[HYSTCTR] = 00
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
Min.
1.71
—
—
V_SS – 0.3
—
—
—
—
—
Typ.
—
—
—
—
—
5
10
20
30
Max.
3.6
200
20
V_DD
20
—
—
—
—
V_CMPOh
V_CMPOl
t_DHS
t_DLS
I_DAC6b
INL
DNL
Output high
Output low
Propagation delay, high-speed mode (EN=1,
PMODE=1)
Propagation delay, low-speed mode (EN=1,
PMODE=0)
Analog comparator initialization delay²
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
6-bit DAC differential non-linearity
V_DD – 0.5
—
—
—
—
0.5
20
50
200
80
250
600
—
—
40
—
7
—
–0.5
—
0.5
–0.3
—
0.3
Unit
V
μA
μA
V
mV
mV
mV
mV
mV
V
V
ns
ns
μs
μA
LSB³
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to V_DD-0.6V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = V_reference/64
K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.
38
Freescale Semiconductor, Inc.