K11P121M50SF4 Datasheet, PDF (48/59 Pages) Freescale Semiconductor, Inc – K11 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
DS10
DS15
DS13
First data
DS14
First data
DS12
Data
Data
DS9
DS11
Last data
DS16
Last data
Figure 19. DSPI classic SPI timing — slave mode
6.8.3 I²C switching specifications
See General switching specifications.
6.8.4 UART switching specifications
See General switching specifications.
6.8.5 Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 37. I2S/SAI master mode timing
Num.
S1
S2
S3
S4
S5
S6
S7
Characteristic
Operating voltage
I2S_MCLK cycle time
I2S_MCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
I2S_TX_BCLK to I2S_TXD valid
Min.
1.71
40
45%
80
45%
—
0
—
Table continues on the next page...
Max.
3.6
—
55%
—
55%
15
—
15
Unit
V
ns
MCLK period
ns
BCLK period
ns
ns
ns
K11 Sub-Family Data Sheet Data Sheet, Rev. 3, 08/2012.
48
Freescale Semiconductor, Inc.