MC68HC912D60 Datasheet, PDF (52/432 Pages) Freescale Semiconductor, Inc – M68HC12 Microcontrollers

Freescale Semiconductor, Inc.
Pinout and Signal Descriptions
Table 3-2. 68HC(9)12D60 Signal Description Summary
Pin Number
Pin Name
80-pin 112-pin
Description
XIRQ
40
56
Provides a means of requesting asynchronous nonmaskable interrupt
requests after reset initialization
SMODN/BK
GD/TAGHI
15
Single-wire background interface pin is dedicated to the background debug
23
function. During reset, this pin determines special or normal operating
mode. Pin function TAGHI used in instruction tagging. See Development
Support.
PW[3:0] 80, 1–3 112, 1–3 Pulse Width Modulator channel outputs.
SS
70
96
Slave select output for SPI master mode, input for slave mode or master
mode.
SCK
69
95
Serial clock for SPI system.
SDO/MOSI 68
94
Master out/slave in pin for serial peripheral interface
SDI/MISO
67
93
Master in/slave out pin for serial peripheral interface
TxD1
66
92
SCI1 transmit pin
RxD1
65
91
SCI1 receive pin
TxD0
64
90
SCI0 transmit pin
RxD0
63
89
SCI0 receive pin
IOC[7:0]
14–11,
7–4
18–15, 7–4
Pins used for input capture and output compare in the timer and pulse
accumulator subsystem.
AN1[7:0]
N/A
84/82/80/78/
76/74/72/70
Analog
inputs
for
the
analog-to-digital conversion module
1
AN0[7:0]
60–53
83/81/79/77/
75/73/71/69
Analog
inputs
for
the
analog-to-digital conversion module
0
TxCAN
72
104 MSCAN transmit pin
RxCAN
73
105 MSCAN receive pin
KWG[6:0]
8 (KWG4
only)
9–11, 19–22
Key wake-up and general purpose I/O; can cause an interrupt when an input
transitions from high to low. On 80-pin QFP all 8 I/O should be initialised.
PGUPD
(1)
13
Defines if I/O port resistive load is a pull-up or a pull-down, when enabled.
KWH[7:0]
24 (KWH4
only)
32–35,
49–52
Key wake-up and general purpose I/O; can cause an interrupt when an input
transitions from high to low. On 80-pin QFP all 8 I/O should be initialised.
PHUPD
(2)
41
Defines if I/O port resistive load is a pull-up or a pull-down, when enabled.
1. In the 80-pin version PGUPD is connected internally to VDD
2. In the 80-pin version PHUPD is connected internally to VSS
Advance Information
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Pinout and Signal Descriptions
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68HC(9)12D60 — Rev 4.0
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