MC68HC912D60 Datasheet, PDF (306/432 Pages) Freescale Semiconductor, Inc – M68HC12 Microcontrollers

Freescale Semiconductor, Inc.
MSCAN Controller
node. In this state the msCAN12 ignores the bit sent during the ACK
slot of the CAN frame acknowledge field to insure proper reception of
its own message. Both transmit and receive interrupts are generated.
0 = Normal operation
1 = Activate loop back self test mode
WUPM — Wake-Up Mode
This flag defines whether the integrated low-pass filter is applied to
protect the msCAN12 from spurious wake-ups (see Programmable
Wake-Up Function).
0 = msCAN12 will wake up the CPU after any recessive to
dominant edge on the CAN bus.
1 = msCAN12 will wake up the CPU only in the case of dominant
pulse on the bus which has a length of at least approximately
T_wup.
CLKSRC — msCAN12 Clock Source
This flag defines which clock source the msCAN12 module is driven
from (only for system with CGM module; see Clock System, Figure
17-7).
0 = The msCAN12 clock source is EXTALi.
1 = The msCAN12 clock source is SYSCLK, twice the frequency of
ECLK.
NOTE: The CMCR1 register can be written only if the SFTRES bit in CMCR0 is
set.
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MSCAN Controller
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68HC(9)12D60 — Rev 4.0
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