MC68HC912D60 Datasheet, PDF (132/432 Pages) Freescale Semiconductor, Inc – M68HC12 Microcontrollers

Freescale Semiconductor, Inc.
Resets and Interrupts
required to complete the instruction. Some of the longer instructions can
be interrupted and will resume normally after servicing the interrupt.
When the CPU begins to service an interrupt, the instruction queue is
cleared, the return address is calculated, and then it and the contents of
the CPU registers are stacked as shown in Table 9-2.
Table 9-2. Stacking Order on Entry to Interrupts
Memory Location
SP – 2
SP – 4
SP – 6
SP – 8
SP – 9
CPU Registers
RTN_H : RTN_L
Y_H : Y_L
X_H : X_L
B:A
CCR
After the CCR is stacked, the I bit (and the X bit, if an XIRQ interrupt
service request is pending) is set to prevent other interrupts from
disrupting the interrupt service routine. The interrupt vector for the
highest priority source that was pending at the beginning of the interrupt
sequence is fetched, and execution continues at the referenced location.
At the end of the interrupt service routine, an RTI instruction restores the
content of all registers from information on the stack, and normal
program execution resumes.
If another interrupt is pending at the end of an interrupt service routine,
the register unstacking and restacking is bypassed and the vector of the
interrupt is fetched.
9.9 Customer Information
Before disabling an interrupt using a local interrupt control bit, set the I
mask bit in the CCR. Failing to do so may cause an SWI interrupt to be
fetched instead of the vector for the interrupt source that was disabled.
Advance Information
132
Resets and Interrupts
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68HC(9)12D60 — Rev 4.0
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