MC68HC912D60 Datasheet, PDF (166/432 Pages) Freescale Semiconductor, Inc – M68HC12 Microcontrollers

Clock Functions
Freescale Semiconductor, Inc.
Bit 7
6
5
4
0
BCSP
BCSS
0
RESET:
0
0
0
0
CLKSEL — Clock Generator Clock select Register
3
2
1
Bit 0
0
MCS
0
0
0
0
0
0
$003D
Read and write anytime. Exceptions are listed below for each bit.
BCSP and BCSS bits determine the clock used by the main system
including the CPU and buses.
BCSP — Bus Clock Select PLL
0 = SYSCLK is derived from the crystal clock or from SLWCLK.
1 = SYSCLK source is the PLL.
Cannot be set when PLLON = 0. In limp-home mode, the output of
BCSP is forced to 1, but the BCSP bit reads the latched value.
BCSS — Bus Clock Select Slow
0 = SYSCLK is derived from the crystal clock EXTALi.
1 = SYSCLK source is the Slow clock SLWCLK.
This bit has no effect when BCSP is set.
MCS — Module Clock Select
0 = M clock is the same as PCLK.
1 = M clock is derived from Slow clock SLWCLK.
This bit determines the clock used by the ECT module and the baud
rate generators of the SCIs. In limp-home mode, the output of MCS is
forced to 0, but the MCS bit reads the latched value.
Advance Information
166
Clock Functions
For More Information On This Product,
Go to: www.freescale.com
68HC(9)12D60 — Rev 4.0
MOTOROLA