MC68HC912D60 Datasheet, PDF (358/432 Pages) Freescale Semiconductor, Inc – M68HC12 Microcontrollers

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The scope of comparison can be expanded by ignoring the least
significant byte of address or data matches.
The scope of comparison can be limited to program data only by setting
the BKPM bit in breakpoint control register 0.
To trace program flow, setting the BKPM bit causes address comparison
of program data only. Control bits are also available that allow checking
read/write matches.
Bit 7
6
5
4
3
2
1
Bit 0
BKEN1 BKEN0 BKPM
0
BK1ALE BK0ALE
0
0
RESET:
0
0
0
0
0
0
0
0
BRKCT0 — Breakpoint Control Register 0
$0020
Read and write anytime.
This register is used to control the breakpoint logic.
BKEN1, BKEN0 — Breakpoint Mode Enable
Table 19-9. Breakpoint Mode Control
BKEN1 BKEN0
Mode Selected
BRKAH/L Usage BRKDH/L Usage R/W
0
0 Breakpoints Off
—
—
—
0
1 SWI — Dual Address Mode
Address Match Address Match No
1
0 BDM — Full Breakpoint Mode Address Match
Data Match
Yes
1
1 BDM — Dual Address Mode Address Match Address Match Yes
Range
—
Yes
Yes
Yes
BKPM — Break on Program Addresses
This bit controls whether the breakpoint will cause a break on a match
(next instruction boundary) or on a match that will be an executable
opcode. Data and non-executed opcodes cannot cause a break if this
bit is set. This bit has no meaning in SWI dual address mode. The
SWI mode only performs program breakpoints.
0 = On match, break at the next instruction boundary
1 = On match, break if the match is an instruction that will be
executed. This uses tagging as its breakpoint mechanism.
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68HC(9)12D60 — Rev 4.0
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