K20P81M100SF2_1109 Datasheet, PDF (52/75 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
6.6.3.2 12-bit DAC operating behaviors
Table 33. 12-bit DAC operating behaviors
Symbol Description
I_{DDA_DACL} Supply current — low-power mode
P
I_{DDA_DAC} Supply current — high-speed mode
HP
t_DACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
t_DACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
t_CCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-speed
mode
V_dacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
V_dacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
INL Integral non-linearity error — high speed
mode
DNL
Differential non-linearity error — V_DACR > 2
V
DNL
Differential non-linearity error — V_DACR =
VREF_OUT
V_OFFSET Offset error
E_G Gain error
PSRR Power supply rejection ratio, V_DDA > = 2.4 V
T_CO Temperature coefficient offset voltage
T_GE Temperature coefficient gain error
Rop Output resistance load = 3 kΩ
SR Slew rate -80h→ F7Fh→ 80h
• High power (SP_HP)
• Low power (SP_LP)
Min.
—
—
—
—
—
—
V_DACR
−100
—
—
—
—
—
60
—
—
—
1.2
0.05
Typ.
—
—
100
15
0.7
—
—
—
—
—
±0.4
±0.1
3.7
0.000421
—
1.7
0.12
Max.
150
700
200
30
1
100
V_DACR
±8
±1
±1
±0.8
±0.6
90
—
—
250
—
—
CT Channel to channel cross talk
BW 3dB bandwidth
• High power (SP_HP)
• Low power (SP_LP)
—
—
-80
550
—
—
40
—
—
Unit
μA
μA
μs
μs
μs
mV
mV
LSB
LSB
LSB
%FSR
%FSR
dB
μV/C
%FSR/C
Ω
V/μs
dB
kHz
Notes
1
1
1
2
3
4
5
5
6
1. Settling within ±1 LSB
2. The INL is measured for 0+100mV to V_DACR−100 mV
3. The DNL is measured for 0+100 mV to V_DACR−100 mV
4. The DNL is measured for 0+100mV to V_DACR−100 mV with V_DDA > 2.4V
5. Calculated by a best fit curve from V_SS+100 mV to V_DACR−100 mV
K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
52
Freescale Semiconductor, Inc.