K20P81M100SF2_1109 Datasheet, PDF (24/75 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
Table 14. JTAG full voltage range electricals (continued)
Symbol
J3
Description
TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
Min.
Max.
Unit
50
—
ns
25
—
ns
12.5
—
ns
J4
TCLK rise and fall times
J5
Boundary scan input data setup time to TCLK rise
J6
Boundary scan input data hold time after TCLK rise
J7
TCLK low to boundary scan output data valid
J8
TCLK low to boundary scan output high-Z
J9
TMS, TDI input data setup time to TCLK rise
J10
TMS, TDI input data hold time after TCLK rise
J11
TCLK low to TDO data valid
J12
TCLK low to TDO high-Z
J13
TRST assert time
J14
TRST setup time (negation) to TCLK high
—
3
ns
20
—
ns
0
—
ns
—
25
ns
—
25
ns
8
—
ns
1.4
—
ns
—
22.1
ns
—
22.1
ns
100
—
ns
8
—
ns
TCLK (input)
J2
J3
J3
J4
J4
Figure 5. Test clock input timing
K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
24
Freescale Semiconductor, Inc.