English
Language : 

K20P81M100SF2_1109 Datasheet, PDF (27/75 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet
Peripheral operating requirements and behaviors
Table 15. MCG specifications (continued)
Symbol Description
Min.
FLL
ffll_ref FLL reference frequency range
31.25
fdco
DCO output
Low range (DRS=00)
20
frequency range
640 × ffll_ref
Mid range (DRS=01)
40
1280 × ffll_ref
Mid-high range (DRS=10)
60
1920 × ffll_ref
High range (DRS=11)
80
2560 × ffll_ref
fdco_t_DMX3 DCO output
2
frequency
Low range (DRS=00)
—
732 × ffll_ref
Mid range (DRS=01)
—
1464 × ffll_ref
Mid-high range (DRS=10)
—
2197 × ffll_ref
High range (DRS=11)
—
2929 × ffll_ref
Jcyc_fll FLL period jitter
—
• fVCO = 48 MHz
• fVCO = 98 MHz
—
tfll_acquire FLL target frequency acquisition time
—
PLL
fvco
VCO operating frequency
48.0
Ipll
PLL operating current
• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
—
2 MHz, VDIV multiplier = 48)
Ipll
PLL operating current
• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =
—
2 MHz, VDIV multiplier = 24)
fpll_ref PLL reference frequency range
2.0
Jcyc_pll PLL period jitter (RMS)
• fvco = 48 MHz
—
• fvco = 100 MHz
—
Typ.
Max.
Unit
—
20.97
39.0625
25
kHz
MHz
41.94
50
MHz
62.91
75
MHz
83.89
100
MHz
23.99
—
MHz
47.97
—
MHz
71.99
—
MHz
95.98
—
MHz
180
—
ps
150
—
—
1
ms
—
100
MHz
1060
—
µA
600
—
µA
—
4.0
MHz
120
—
ps
50
—
ps
Notes
2, 3
4, 5
6
7
7
8
Table continues on the next page...
K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
27