K20P81M100SF2_1109 Datasheet, PDF (23/75 Pages) Freescale Semiconductor, Inc – K20 Sub-Family Data Sheet

6.1.2
Peripheral operating requirements and behaviors
JTAG electricals
Table 13. JTAG limited voltage range electricals
Symbol
J1
Description
Operating voltage
TCLK frequency of operation
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
Min.
2.7
0
0
0
Max.
3.6
10
25
50
Unit
V
MHz
J2
TCLK cycle period
J3
TCLK clock pulse width
• Boundary Scan
• JTAG and CJTAG
• Serial Wire Debug
1/J1
—
ns
50
—
ns
20
—
ns
10
—
ns
J4
TCLK rise and fall times
J5
Boundary scan input data setup time to TCLK rise
J6
Boundary scan input data hold time after TCLK rise
J7
TCLK low to boundary scan output data valid
J8
TCLK low to boundary scan output high-Z
J9
TMS, TDI input data setup time to TCLK rise
J10
TMS, TDI input data hold time after TCLK rise
J11
TCLK low to TDO data valid
J12
TCLK low to TDO high-Z
J13
TRST assert time
J14
TRST setup time (negation) to TCLK high
—
3
ns
20
—
ns
0
—
ns
—
25
ns
—
25
ns
8
—
ns
1
—
ns
—
17
ns
—
17
ns
100
—
ns
8
—
ns
Symbol
J1
J2
Table 14. JTAG full voltage range electricals
Description
Operating voltage
Min.
1.71
TCLK frequency of operation
• Boundary Scan
0
• JTAG and CJTAG
0
• Serial Wire Debug
0
TCLK cycle period
1/J1
Table continues on the next page...
Max.
3.6
10
20
40
—
Unit
V
MHz
ns
K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Freescale Semiconductor, Inc.
23